Significant advancement has occurred over the years in electronic development and packaging. Integrated circuit density has and continues to increase at a considerable rate. By way of example, high density electronic packaging module having multiple semiconductor chips thereon are quite popular.
One particular arrangement that has been generating interest is a package that permits the integration of logic and memory devices on the same silicon device. However, this arrangement requires larger devices, and has resulted in increased loss in wafer yield. In particular, memory devices generally are of relatively high yield because of the redundancy built into them. Logic devices, on the other hand, are of relative low yield. Accordingly, combining them on the same silicon wafer results in overall yield dependent upon the lower yield of the logic device portion. Accordingly, there remains room for improvement in electronic packaging, especially when combining logic and memory devices.